Integrated circuit memory devices having volatile data storage may need to include refresh control circuits which refresh data stored in memory cells therein. For example, FIG. 1 illustrates a conventional integrated circuit memory device having refresh capability. In particular, FIG. 1 represents a dynamic random access memory (DRAM) device comprising an array 10 of memory cells which store data, a row address buffer 11 which buffers an m-bit row address, a column address buffer 12 which buffers an n-bit column address, a row address decoder 13 which selects word lines in the memory cell array 10 in response to the row address, a column address decoder 14 which selects columns of memory cells in the memory cell array 10 in response to the column address, a data input buffer 15 which receives data and a data output buffer 16 which supplies data to external devices. The DRAM device also includes a sense amplifier 17 connected to bit lines (not shown) of the memory cell array 10, an input/output gate circuit 18 for selectively connecting the bit lines of the memory cell array to data input and output buffers 15 and 16 in response to the outputs of the column decoder, and a chip control circuit 20 which receives a row address strobe signal (/RAS), a column address strobe signal (/CAS) and a write enable signal (/MWE).
Because the DRAM device provides volatile storage of data, a data refresh circuit 30 is provided for regulating refresh operations. During refresh operations, data signals stored in the memory cells are periodically amplified by the sense amplifier 17 and again rewritten into the memory cells. The refresh circuit 30 comprises a refresh timer 31 for generating the timing signals for the periodic refresh operation, a refresh control circuit 32 for controlling the operations associated with refreshing the memory device in response to the timing signals and a refresh address generator 33 for generating internal refresh addresses under the control of the refresh control circuit 32.
There are a couple of conventional techniques for refreshing data within DRAM cells. One technique is referred to as the /RAS-Only Refresh technique (i.e., ROR technique). In accordance with this technique, the refresh operations for the memory cells are performed by activating only the /RAS signal (/RAS=0) while a /CAS (Column Address Strobe) signal is maintained in a precharged level. Under the ROR mode, memory devices are adapted to receive refresh addresses from the exterior for the respective refresh operations, and address buses connected to the memory devices cannot be used for other purposes.
Another widely used technique is referred to as /CAS-before-/RAS refresh (i.e., CBR refresh). Here, when the memory cells are accessed during the period of normal operations, the externally supplied /RAS signal is activated prior to the /CAS signal. But, in order to recognize an entry into the CBR refresh mode, the /CAS signal should become active before the /RAS signal becomes active, as shown in FIG. 4. In other words, before the /RAS signal transitions from a high level to a low level, the /CAS signal transitions from a high level to a low level. Here, the refresh addresses are generated internally by the refresh address generator 33 installed in the DRAM, and external control for the refresh address generator 33 is typically not possible.
Most DRAMs are also provided with a self-refresh mode in order to reduce the amount of current consumed during the refresh operation. An initial cycle of the self-refresh mode is the same as that of the CBR refresh mode. However, in the event both /CAS and /RAS signals are active simultaneously during a predetermined period (for example, 100 .mu.s), a self-refresh operation will be performed to read out data stored in all the memory cells, amplify the data and then restore the data. During this period of operation, normal operations such as read and write operations are interrupted. The refresh timer 31 and the refresh address generator 33 in the DRAM typically operate in response to an internal clock signal and not an external clock signal. However, because the refresh time period of the self-refresh mode is generally set to a longer period than those of different refresh modes (e.g., the self-refresh time period is set to 128 ms (or longer) while the CBR refresh time period is set to 16 ms), the current consumed during self-refresh may be lower than during another refresh period. Conventional integrated circuit memory devices which utilize refresh modes are also disclosed in U.S. Pat. Nos. 4,809,233, 4,939,695, 4,943,960 and 5,315,557.
The time period required for refreshing all the rows of a memory cell array is generally referred to as a refresh cycle time. For example, in a sixteen megabit DRAM having a cell array comprising 2048 rows.times.512 columns.times.16 bits, 2048 rows may be sequentially refreshed during the time interval 128 ms. In this case, the inter-cycle time interval (i.e., the refresh clock period) is approximately 62.5 .mu.s (=128 ms/2048 rows). Thus, a refresh of one row of the array (which may take 80-200 ns) can be performed during each 62.5 .mu.s time interval.
FIG. 2 illustrates a detailed configuration of the refresh address generator 33 and the row address buffer 11 of FIG. 1. Referring to FIG. 2, the refresh address generator 33 comprises m-bit binary ripple counter which comprises toggle flip-flops FF0-FFm-1 connected in series. The refresh address generator 33 generates m-bit refresh addresses CO-Cm-1. The flip-flop FF0 receives LSB control pulse signal CNTP from the refresh control circuit 32 and generates LSB address signal C0 and its complementary signal CT0. The next flip-flop FF1 receives the signal CT0 and generates the higher bit address signal C1 and its complementary signal CT1. Similarly, the remaining flip-flops FF2, FF3, . . . , and FFm-1 respectively receive the complementary address signals from the lower bit flip-flops and generate the corresponding bit address signals and their complementary address signals.
The refresh control circuit 32 controls the flip-flops FF0-FFm-1by means of an address output control signal PRCNT so that m-bit refresh addresses C0-Cm-1 can be forwarded from the flip-flops FF0-FFm-1 to the row address buffer 11. The address bit signals CO-Cm-1 output from the flip-flops FF0-FFm-1 are respectively supplied to the corresponding buffers AB0-ABm-1 in the row address buffer 11.
In general, although a plurality of refresh modes implemented in a single DRAM have different refresh times (for example, 4-256 ms) respectively, all refresh modes are provided with identical refresh cycles. However, to provide memory devices which require less power, attempts have been made to reduce the self-refresh current by designing a cycle of the self-refresh mode to be shorter than that of other refresh modes (for example shorter than the CBR refresh mode).
FIG. 3 illustrates relations between the generated refresh address signals and the word lines selected by the address signals under the CBR refresh mode and the self-refresh mode in the event the numbers of cycles per refresh period in the CBR refresh mode and the self-refresh mode are respectively set at 2K and 1K. For convenience of explanation, as shown in FIG. 3, it is assumed that memory cell array 10 includes two memory banks BANK1 and BANK2, to which a total of 2.times.1024 rows and word lines are provided. To address these 2048 rows, a row address of eleven (11) bits is required. During a CBR refresh mode of a 2K cycle, as shown in the upper part of FIG. 3, the refresh address generator 33 generates internal refresh addresses 00h (=00000000000) through 7FFh (=11111111111) sequentially. By so doing, word lines WL0-WL2047 of the two memory banks BANK1 and BANK2 are sequentially selected. On the other hand, if a self-refresh mode of a 1K cycle is provided, as shown in the lower part of FIG. 3, the refresh address generator 33 will generate the addresses 000h (=00000000000) through 3FFh (=01111111111) sequentially to select each pair of word lines WL0 and WL1024, WL1 and WL1025, . . . , and WL1023 and WL2047 in order. That is, a pair of word lines are simultaneously selected per refresh cycle in the self-refresh mode.
However, if the refresh cycle during the self-refresh mode is smaller than that of the CBR refresh mode, then at least one row or word line will not be selected when (1) only the self-refresh operation is performed, (2) the self-refresh operation is performed after completion of at least one cycle of a CBR refresh operation, or (3) another self-refresh operation is performed after completion of the prior self-refresh operation and at least one cycle of a CBR refresh operation. This means that some memory cells may not be refreshed properly if any of the conditions (1)14 (3) occur.
To illustrate, it is assumed that the CBR refresh operation of a 2K cycle and the self-refresh operation of a 1K cycle are performed in series and the initial address of the refresh address generator 33 is set to 000h. As described above, in order to change the refresh mode in a certain semiconductor memory device into the self-refresh mode, it is necessary that at least one CBR refresh cycle be performed. That is, when the CBR refresh mode of operation has been initiated and thus the /CAS and /RAS signals are maintained at low levels during a predetermined time period ( e.g. 100 .mu.s) or longer, the refresh mode of the memory device will switch to the self-refresh mode. Since the beginning cycle of the 1K self-refresh mode is the same as that of the 2K CBR refresh mode, the first word line WL0 of the memory block BANK1 shown in FIG. 3 is selected by means of the initial address 000h provided by the refresh address generator 33. Next, the successive self-refresh cycles will be performed and the refresh address generator 33 will generate the addresses 001h, 002h, . . . , 3FFh in sequence. Therefore, pairs of the word line WL1 and WL1025, WL2 and WL1026, . . . , and WL1023 and WL2047 will be selected in turn. As a result, the first word line WL1024 of BANK2 will not be selected during the 1K self-refresh term, but the word line WL1024 will be selected during the following self-refresh term.
As illustrated by FIG. 4, in the event one cycle of the 2K CBR refresh operation is performed and thereafter a 1K self refresh operation is performed, if WL0 of Bank 1 is selected in a 2K CBR cycle then WL1024 of Bank 2 will not be selected. Thereafter, upon entry into a self-refresh mode, WL1 of Bank 1 will be selected, but WL1025 of Bank 2 will not be selected. Next, WL2 in Bank 1 and WL1026 in Bank 2 will be selected, followed by WL3 and WL1027 and so on. Furthermore, as illustrated by FIG. 5, in the event one cycle of the 1K self refresh operation is performed, then one cycle of the 2K CBR refresh operation is performed and then another 1K self refresh operation is performed in sequence, then WL1021, WL1022 or WL2045, WL2046 will not be selected in the CBR and self-refresh entry cycles, respectively, if the self-refresh mode is exited at WL1020 has been selected.
Thus, notwithstanding the above-described integrated circuit memory devices, integrated circuit memory devices having improved refresh mode addressing are required so that rows of memory cells are not skipped when transitioning from one refresh mode to another refresh mode.